Advanced VLSI Engineering, Inc.

 

Pierre Dermy

 

Office phone and fax:    (775) 970-5473

Cellular phone:              (530) 391-2978

pierre@advlsi.com

 

 

 

Experience and capabilities

 

Electronics Engineering and Design Contractor with over 28 years experience in full-custom analog, RF and digital IC and PCB, FPGA-based prototypes, MCU applications.

 

We provide engineering and design contract services focused on time-to-market, accuracy and reliability. Based on detailed project specifications, our solutions include:

• Optimization for high/nA-current, high-speed/low-power, low/high-voltage, noise immunity, device/system size and cost.

• Design for test and manufacturing.

• Proven design flow and cell library to tackle most analog, RF and mixed-signal CMOS and BiCMOS IC.

 

Our consulting services support project teams with:

• Project timeline, technical specifications and documentation.

• Lab-bench and field measurements, prototype testing and debugging.

• Semiconductor, IC packaging and PCB technology evaluation.

• Circuit modeling, yield analysis and improvement.

• Product cost reduction.

 

Since 1986, diligently we have served 35 client companies, mostly in Silicon Valley.

We have built a track record of successful analog and mixed-signal IC designs: RF wireless transceiver, multi-GBps wireline I/O (HSTL, LVCMOS, LVDS, PECL, BTL), HV I/O buffers, SerDes, ADC, video DAC, PLL, frequency synthesizers and clock networks, point-of-load DC voltage converters, power management and distribution IC, analog micropower IC, SRAM, CAM, microprocessor building blocks and integration, FPGA prototypes, embedded MCU applications, IC packages (CSP and MCM), fine-line PCB, signal integrity analysis, EMI-RFI and ESD protection circuits.

CAD/E Tools

Tanner L-Edit Pro, T-SPICE Pro, Mathcad, Sonnet, Comsol Multiphysics, Ansoft Designer, SiSoft Quantum SI, Altium Innovation Station, Electronics Workbench, LabVIEW,
IAR Embedded Workbench and visualSTATE, Icarus Verilog, Alliance VLSI Tools,
Altera Quartus II, Aldec HDL Express, ActivePERL
SolidWorks

Programming languages: C/B/K-Shell, PERL, C, Verilog

 

Recent contract assignments and electronic circuits IP development

 

RFID Tags, ADC: pipelined, flash and SD, DAC, PLL, DC power converters, charge pumps and V/I regulators, RF transceivers, SRAM IC mask layout generator.

 

Consulting on I/O buffers and pad rings (PECL, LVDS, HSTL, LVCMOS, PCI, BTL), ESD and latch-up protection circuits, backplane and PCB signal integrity analysis, IC and POL power distribution, noise immunity, BGA and flip-chip packaging, frequency synthesis, clock distribution networks, circuit timing and testability.

 

List of projects

 

Synchronous SRAM in 0.18mm CMOS, circuit design, IC mask layout, memory block
(128X12 to 8192X64 bits) assembler (Unix B-Shell script and L-Edit UPI macro).

 

Design of a micropower RF transponder for a battery-operated RFID Tag in 0.50mm CMOS process and with MOSFET’s operating in weak inversion.

 

Design of a bipolar OpAmp for EMI application ( VCC 6 V to 30 V, ICC < 15 mA, cap.
load up to 20 nF, DC gain 80 dB, UGB 80 MHz, SR 350 V/µs with CL 50 pF, DC output swing 80 % of VCC ) with power down control.

 

Redesign and IC mask layout of 5V-tolerant I/O Buffers and ESD protection circuit of

a Crystal/RC Oscillator Pad, in a CMOS 0.35mm technology.

 

Design in SOI CMOS 0.13mm technology of programmable voltage generators for VLSI  applications and SRAM with high dynamic load (500mA peak and 500ps transients), combining coarse and fine voltage regulation loops.

 

Design in SOI CMOS 0.13mm technology of HSTL and LVCMOS I/O with analog and digital calibration.

 

Design in SOI CMOS 0.13mm technology of a high-current negative voltage generator
(-2.0V 2.0mA) with smart power regulation: US Patent 6,756,838

 

Novel ESD Protection Circuit for a SOI CMOS 0.13mm technology.

 

Design of a video analog front end in a CMOS 0.25mm technology. Pipelined ADC’s with 8/10bit ENOB, 175/30MSps sampling rate, digital error calibration, programmable input clamp, synchronization pulse detection and HSYNC/VSYNC separation, PLL and frequency synthesizer (input 15-110kHz output 10-175MHz, jitter of 10ps at 10MHz and 200ps at 175MHz).

 

Architecture and first-pass design in a CMOS 0.18mm technology of a SerDes CDR and LVDS parallel bus interface (16bit wide data and 1 clock) with a data transfer rate of 1.56GBytes per second.

 

Design in a BiCMOS 0.80mm technology of a micropower undervoltage detector for battery monitoring in cellular phones and portable equipment (LMS33460).

 

Architecture and first-pass design of a 12bit ADC and data acquisition IC in a silicon BiCMOS 0.50mm technology.  Sampling rate 1GSps, ENOB 11bit, dual port FIFO buffer, open/closed loop auto calibration and BIST modes.

 

IC layout floor-planning, power and clocks distribution networks, place-and-route and

post-layout verification of 2D/3D graphics and video VLSI processors, using Avant! XO,

Planet and Apollo VLSI CAD tools.

 

CMOS 0.35mm I/O buffers and ESD protection circuits. Design for reliability of I/O

periphery and power distribution of VLSI circuits. Packaging and signal integrity issues.

 

Circuit design and IC mask layout of a DLL-based clock distribution IC: PLX EQ6610.

 

TTL-BTL bus transceivers for Futurebus or similar backplane bus applications, designed

in Philips Semiconductor BiCMOS 0.80 mm (QuBiC) technology.

 

BiCMOS cell library for RF communication: bandgap voltage and current reference generators, LNA, mixer, PLL and sigma-delta modulator for fractional N frequency synthesizer, phase/frequency modulator, RF output amplifier.

 

PECL I/O buffers for 3.30V/5.0V operation, 4.0mils pad pitch, ESD protection, latch-up

immunity.

 

Clock distribution network and I/O periphery of Intel PCI-to-ISA and PCI-to-PCI bridges

for laptop PC and docking station.

 

Conversion of a digital camera memory and CCD sensor controller from a XC4000

FPGA to a Chip Express QYH500 gate array. Behavioral and RTL model in VHDL,

logic synthesis, test bench and test suites, fault grading and production test vectors.

 

Management of the VLSI design team implementing a LAN switch for NEC America.

Microarchitecture and test specifications, behavioral and RTL modeling.

 

DRAM Controller for a C-Cube MPEG1 video processor used in a karaoke CDROM

player. Verilog RTL modeling and translation of behavioral model written in C,

Synopsys logic synthesis into a CMOS standard cell library, test suite.

 

CMOS cell library implementing the JTAG 1149.1 IEEE standard. Post-layout timing

analysis of R3081, using Dracula LPE, Timemill and HSPICE. Netlist parser and path

extraction written in C and Unix C shell, sed and awk scripts.

 

CMOS circuit design, low-power and high-speed tradeoffs, logic optimization on the

compaction of the Intel Pentium for laptop PCs.

 

Design of the Instruction Cache for the Intel Pentium (P5 Rev. 1). Consulting on

BiCMOS technology and circuit design techniques.

 

Circuit design and logic optimization on Intel H4C/80486SL, 80486SX.

 

Design of a PLL in CMOS 0.80mm technology, 100MHz clock synthesizer and logic

synchronization. CMOS bandgap regulator, programmable loop filter and output

frequencies, lock detection.

 

Cache controller tag memory of the Intel 80386SL.

 

Hardware behavioral modeling and test benches using Verilog and C-PLI from the

component data sheets and functional specifications of the TMS44C251 Video RAM,

WD33C93 SCSI Controller, Am7990 Ethernet LAN Controller.

 

Circuit design and IC layout of a BiCMOS gate array master and programmable I/O

buffers in a Cypress Semiconductor BiCMOS 0.80mm technology.

 

Design of a 4KX4 ECL SRAM in Cypress Semiconductor BiCMOS 0.80mm technology.

 

CAM-based Translation Lookaside Buffer for Fujitsu Sparc chipset, in CMOS 1.0mm

and 0.80mm technologies.

 

Design of the hardware and PCB for a X-Terminal, using the 80386 CPU, 80387 FP coprocessor, cache memory controller, Am7990 Ethernet LAN Controller, Chips & Technologies PC-AT chipset, National Semiconductor DP8500 Graphics Engine.

 

Design of a Smart Card system: EEPROM-based data carrier, RF and IR

transceivers, LCD, data I/O controller using the Motorola MC68HC05/11 MCU.

Prototype breadboard and firmware development.

 

Design of a GDT Silicon Compiler library for embedded microcontroller applications

using the 8051 instruction set.

 

BiCMOS cell library and design flow, Dracula DRC, ERC, LVS and LPE rules and

set-up files.

 

Design of 256Kbits and 64Kbits SRAM in BiCMOS 1.0-mm technology.

 

Design of a RAMDAC equivalent to the Brooktree Bt458, with 125MHz operating frequency, in a CMOS 1.25-mm two-metal technology.

 

Design of a CMOS 1Mbit EPROM (27C210 - 64KX16).

 

System and logic design of a Virtual Instruction Processor, microcoded to emulate

the instruction sets of the 68020 and 80386 microprocessors.

System and logic design of a MIL-STD-1553B remote terminal and controller, bus interface and protocol management unit.

 

Logic, circuit design and IC layout of MIL-STD-1750A CMOS 16-bit microprocessor, with FPU and interrupt controller for real-time applications.

 

Design of mixed-signal, analog and digital CMOS IC for ordnance electronics.

Low-power watchdog and timer, integrated RF field rectifier and power module, filters, transceiver, frequency and phase modulator and demodulator, polynomial counters, and output conditioner.

 

Design of a mixed-signal CMOS IC to reduce the BOM and cost of Rohm PBX equipment.

 

Logic and circuit design and IC layout of bipolar Schottky TTL, ECL and I3L IC cell

libraries, SRAM, F9450 microprocessor, high-speed bus interface, timer and ADC

 

Design and fabrication of CMOS IC and Si solar cells. Si process development:

photomasking, oxidation, dry and wet etching, ion implantation and thermal diffusion,

Al metallization. MOS device characterization and modeling.

 

Analog test instrumentation, Automation of measurements using a DEC LSI-11/02

microcomputer, an ADAC-1000 data acquisition board and a GPIB-488 interface

module.

 

System programming in Pascal, C and assembly language.

 

Design of a Gas Chromatography Controller, using an Intel 8748 Microcontroller, and

Analog Devices ADC.

 

Prototype breadboard and firmware development: test and calibration, sequencing, PID

control loop, data acquisition, formatting and display.

 

Data acquisition and control system for hydraulic pumps, using an HP9825, temperature,

vibration and pressure transducers and electronic measurement equipment. Application

program in BASIC.

 

Characterization and modeling of GaAs MESFET and microwave IC.

 

Microfabrication and characterization of thin-film heterojunction GaAsInP lasers and

fiber-optics coupler. Liquid-phase epitaxy, photomasking and wet etching.

Education

 

Diplome d'Ingenieur (BSEE-MSEE)

Ecole Superieure d'Ingenieurs en Electronique et Electrotechnique

Paris, France - 1980.

 

MSEE

University of Cincinnati, Ohio - 1981.

 

 

Research work

 

* GaAs device modeling, digital and RF analog circuits.

* GaAsInP semiconductor laser.

* Data acquisition and electronic control circuits.

* Si analog IC design and processing, semiconductor device manufacturing.

* Fabrication of MOS tunnel diodes and solar cells.

 

MSEE Thesis

 

"MOS Interface Trapped Charge Characterization Using The AC Conductance

Technique"

 

 

List of companies since Q4 1986

 

Power^eLab Ltd – Hong Kong

Alien Technology Corp. - Morgan Hill, CA

ZiLOG, Inc. - San Jose, CA

Advanced Hardware Architectures, Inc. - Pullman, WA

Sebring Systems, Inc. - Campbell, CA

Arcadia Design Systems, Inc. - Santa Clara, CA

Aureal Semiconductor, Inc. - Fremont, CA

3Dfx Interactive, Inc. - San Jose, CA

Equator Technologies, Inc. - Campbell, CA

Cascade Design Automation Corp. - Seattle, WA

PLX Technology, Inc. - Sunnyvale, CA

Intel Corporation, Mobile and Home Computing Group - Santa Clara, CA

Intel Corporation, Microprocessor Group - Santa Clara, CA

Philips Semiconductor, Communication Products - Sunnyvale, CA

Philips Semiconductor, Multimedia PC - Mountain View, CA

Oak Technology, Inc. - Sunnyvale, CA

NEC America, Inc. - San Jose, CA

C-Cube Microsystems - Milpitas, CA

OASIC Technology, Inc. - Santa Clara, CA

D'Ombre Systems, Inc. - Campbell, CA

Vertex Semiconductor Corp. - San Jose, CA

Chips and Technologies, Inc. - San Jose, CA

Matra Design Semiconductor - Santa Clara, CA

Aspen Semiconductor - San Jose, CA

Ardent Computer Corp. - Sunnyvale, CA

Fujitsu Microelectronics, Inc. - San Jose, CA

Interfirm Graphic Systems, Inc. - Santa Clara, CA

Quantic Industries, Inc. - San Carlos, CA

Raytheon, Semiconductor Division - Mountain View, CA

Advanced Micro Devices - Sunnyvale, CA

Compression Lab, Inc. - San Jose, CA

American Information Technology, Inc. - Cupertino, CA

Catalyst Semiconductor Corp. - Santa Clara, CA

 

Prior clients

 

Intersmat S.A. - Chelles-Les-Coudreaux, France

Bergeron S.A. - Paris, France

 

 

Direct/W4 employers

 

T-RAM, Inc. - San Jose, CA

nDSP Corp., Campbell - San Jose, CA

National Semiconductor Corp., Analog Products – Sunnyvale and Grass Valley, CA

Performance Semiconductor Corp.- Sunnyvale, CA

IMP, Inc. - San Jose, CA

Data General Corp. Semiconductor Division - Sunnyvale, CA

Fairchild Semiconductor Corp. R&D Labs - Palo Alto, CA

 

 

Membership

 

Institute of Electrical and Electronic Engineers (IEEE) since 1979

Technology Alliance Bridge: www.tabridge.com, Silicon Valley since 1996