ADVLSI
Analog & Digital
Very Large Scale Integrated Circuits
USA-based Experience and Capabilities
* Full-custom IC, ASIC, PCB, FPGA, MCU, MPU and Memory designs.
* Wide range of applications, including high-performance RF, Analog
and Digital electronics,
optimization for high-speed or low-power.
* Design and manufacturing costs reduction.
* Design for Testability and Manufacturability.
* Detailed documentation for Quality Assurance and Contract
Manufacturing.
Since
1986, diligently served and designed for more than 40 companies, mostly in
Silicon Valley.
Track record of successful analog and mixed-signal
IC designs: RF wireless transceivers, multi-Gbps
wireline I/O (HSTL, LVCMOS, LVDS, PECL, BTL), HV I/O Buffers, SerDes, ADC, Video DAC, PLL,
DC voltage converters, power management and distribution, analog micropower IC, SRAM's, EPROM,
Microprocessors (MPU), FPGA prototypes and embedded Microcontroller (MCU) applications, 2.5/3D
IC packages (CSP and MCM), fine-line PCB, signal integrity, EMI- RFI and ESD protection.
Team building of experts in VLSI, MEMS, 2.5/3D IC packaging, Mechatronics,
RF antennas,
microwave hardware, wireless communication protocols (WiFi, LTE, 5G), embedded
processors,
software development for real-time applications, Data Analytics and Artificial
Intelligence.
We are well prepared to solve new product development challenges for:
the Internet-of-Things, Wireless Sensor Networks and Remote Control with micro-actuators.
CAD
tools: Tanner EDA VLSI Pro
(L-Edit, T-SPICE), HiPer Silicon, Alliance VLSI
Tools,
Icarus Verilog, Verilog-A, Altera Quartus II, Aldec HDL Express,
Altium Designer, NI LabVIEW,
NI Electronics Workbench, Mathcad,
IAR Embedded Workbench, Comsol Multiphysics, Sonnet,
SolidWorks.
Programming languages: C, UNIX Shell, Sed, Perl, AWK, Verilog, Verilog-A.
Project management tools: MS Project, MS Office Suite.
Portfolio
of consulting service, product and IP development projects
RFID Tags, ADC: pipelined, flash and SD, DAC, PLL, DC power converters, charge pumps and V/I
regulators, RF transceivers, SRAM, CAM, non-volatile memories, Network processors.
Consulting on I/O buffers and pad rings (PECL, LVDS, HSTL, LVCMOS, PCI, BTL), ESD and latch-up
protection circuits, backplane and PCB signal integrity analysis, IC and PofL power distribution, noise
immunity, BGA and flip-chip packaging, frequency synthesis, clock distribution networks, circuit timing
and testability, IofT-enabling hardware and software tools.
List of projects from 2000 to present
Most recent:
* Consulting, IC design and technology development in CMOS 30/20 nm
technology for Digital, and
Analog Mixed-Signals applications, integrating a new type of Si devices to
produce better integration
density than a FinFET-based 16 nm CMOS technology.
* Design of VLSI Digital, SRAM, CAM and Analog circuit cells to
show the feasibility.
* VLSI CAE/D method and development plans. Device
physics and models.
* VLSI fabrication plan with CMOS Si IC foundry,
including new Si die processing steps, photomask
and circuit design rules.
* Product and IP development plan for Internet-of-Things, RF radio
and communication processor
for 5G, sensor interface circuits, communication network processor based on
open source computing
library, and cybersecurity hardware engine.
* International patent application filed, with most claims
approved: WO2016057973-A1.
Other work and projects, with most designs released
to production:
[56] Consulting
on encapsulated power supplies and drivers of LED lamps, circuit simulation
of electrothermal effects. System
architecture, design partitioning: HW-SW, PCB and IC
partition, MCU and
development tools. Definition of DFTM flow and test benches.
Solutions and impact of 3-D integration and packaging.
[55] Consulting
on the micro-architecture, circuit design and development plan of
photonic-based
transceivers for Hybrid Memory Cube.
[54] Consulting
on the technologies and markets for Passive Optical Network components: FTTH/X
deployment, integration of fiber-optic connectivity into
PC’s and Si dice.
[53] Consulting
on wireless electrical power converter and transceiver for medical implant.
[52] CMOS
RF Transceiver 5GHz, concept design in 0.13 mm CMOS MiM-L&C.
[51] Synchronous
SRAM in 0.13mm CMOS, circuit design, IC mask layout,
memory block assembler
proven by two blocks (128X12 to 8192X64 bits) embedded in
product released to production;
SRAM assembler/compiler program written in Perl script and L-Edit
UPI macro.
[50] Design of a micropower
RF transponder for a battery-operated RFID Tag in 0.50 mm CMOS
process and with
MOSFET’s operating in weak inversion.
[49] Design of a bipolar OpAmp
for EMI application ( VCC 6 V to 30 V, ICC
< 15 mA, cap. Load
up to 20 nF, DC gain 80 dB, UGB 80 MHz, SR 350 V/µs with CL
50 pF, DC output swing 80 %
of VCC
) with power down control.
[48] Redesign and IC mask layout of 5V-tolerant
I/O Buffers and ESD protection circuit of
a
Crystal/RC Oscillator Pad, in a CMOS 0.35 mm technology.
[47] Design
in SOI CMOS 0.13mm technology of programmable voltage
generators for VLSI
applications and SRAM
with high dynamic load (500 mA peak and 500 ps
transients),
combining coarse and fine voltage regulation loops.
[46] Design
in SOI CMOS 0.13mm technology of HSTL and LVCMOS I/O with
calibration.
[45] Design
in SOI CMOS 0.13mm technology of a high-current negative
voltage (-2.0V 2.0mA)
generator with smart
power regulation: US Patent 6,756,838
(invented the concept and technique,
most of the detailed design, guided the team to write the
patent).
[44] Novel
ESD Protection Circuit for dense VLSI dice in a SOI CMOS 0.13 mm technology:
US
Patent 7,187,530 (invented the concept and technique, most of the detailed design
guided
the team to write the patent).
[43] Design of a video analog front end in a
CMOS 0.25 mm technology. Pipelined ADC’s with 8/10-bit
ENOB, 175/30 MSps
sampling rate, digital error calibration, programmable input clamp, detection
of
synchronization pulse and HSYNC/VSYNC separation, PLL and frequency
synthesizer.
[42] Architecture
and first-pass design in a CMOS 0.18 mm technology of a SerDes CDR and LVDS
parallel bus interface (16-bit wide data and 1 clock) with a
data transfer rate of 1.56 Gbytes/second.
[41] Design in a BiCMOS 0.80 mm technology of a micropower undervoltage/end-of-charge detector
for battery monitoring in cellular phones and portable equipment (LMS33460). Pure Analog IC
design. First prototype qualified to full technical specifications, and photomask set transferred
to large-scale production at first ICML tapeout.
[40] Architecture
and first-pass design of a 12bit ADC and data acquisition IC in a Silicon BiCMOS
technology (0.80 mm scalable to 0.50 mm with no redesign). Sampling
rate 1GSps, 11-bit ENOB,
dual port FIFO buffer, open/closed loop auto calibration and
BIST modes.
List
of projects prior to 2000
[39] IC
layout floor-planning, power and clocks distribution networks, place-and-route
and post-layout
verification of 2D/3D graphics and video VLSI processors,
using Avant! XO, Planet and Apollo
VLSI CAD tools.
[38] CMOS
0.35mm I/O buffers and ESD protection circuits. Design
for reliability of I/O periphery
and power distribution of VLSI circuits. Packaging
and signal integrity issues.
[37] Circuit
design and IC mask layout of a DLL-based clock distribution IC: PLX EQ6610.
[36] TTL-BTL
bus transceivers for Futurebus or similar backplane
bus applications, designed in
the Philips Semiconductor BiCMOS
0.80 mm (QuBiC) technology.
[35] BiCMOS cell library for RF communication: bandgap voltage
and current reference generators,
LNA,
mixer, PLL and sigma-delta modulator for fractional-N frequency synthesizer,
phase
and frequency modulator, RF output amplifier.
[34] PECL
I/O buffers for 3.30 V / 5.0 V operation, 4.0 mils pad
pitch, with excellent ESD protection
and latch-up immunity, programmable impedance matching and
IC calibration.
Clock
distribution network and I/O periphery of Intel PCI-to-ISA and PCI-to-PCI
bridges
for laptop PC and docking station.
[33] Conversion
of a digital camera memory and CCD sensor controller from a XC4000 FPGA
to a Chip Express QYH500 gate array. Behavioral and RTL
model in VHDL, logic synthesis,
test bench and test suites, fault grading and production test
vectors.
[32] Management
of the VLSI design team implementing a LAN switch for NEC America.
Microarchitecture and test specifications, behavioral and RTL
modeling.
[31] DRAM
Controller for a C-Cube MPEG1 video processor used in a karaoke CDROM player.
Verilog
RTL modeling and translation of behavioral model written in C, Synopsys logic
synthesis into a CMOS standard cell library, test bench and
test suite.
[30] CMOS
cell library implementing the JTAG 1149.1 IEEE standard. Post-layout timing
analysis
of R3081, using Dracula LPE, Timemill
and Hspice. Netlist parser and path extraction
written
in C and Unix C-shell, sed and awk scripts.
[29] CMOS
circuit design, low-power and high-speed tradeoffs, optimization of Logic and
specific
blocks for the compaction of the Intel Pentium for laptop
PCs.
[28] Design
of the Instruction Cache for the Intel Pentium (P5 Rev. 1).
Consulting on BiCMOS technology and
circuit design techniques.
[27] Circuit
design and logic optimization of the Intel H4C/80486SL, 80486SX.
[26] Design
of a PLL in CMOS 0.80mm technology, 100MHz clock
synthesizer, Logic synchronizer.
bandgap regulator, programmable loop filter and output
frequencies, lock detection.
[25] Cache
controller tag memory of the Intel 80386SL: first microprocessor integrating
cache
and DRAM controllers, the full AT chipset. MPU released to
production at first ICML-TO
and elected product of the year by Fortune Magazine.
[24] Hardware
behavioral modeling and test benches using Verilog and C-PLI from the component
data sheets and functional specifications of the TMS44C251
Video RAM, WD33C93 SCSI
Controller, Am7990 Ethernet LAN Controller.
[23] Circuit
design and IC layout of a BiCMOS gate array master
and programmable I/O buffers
in Cypress Semiconductor BiCMOS
0.80 mm technology.
[22] Design
of a 4KX4 ECL SRAM in Cypress Semiconductor BiCMOS
0.80 mm technology.
[21] Binary
CAM-based Translation Lookaside Buffer for Fujitsu SPARC chipset, in CMOS 1.0 mm
and 0.80 mm technologies.
[20] Design
of the hardware and PCB for a X-Terminal, using the
80386 CPU, 80387 Floating Point
coprocessor, cache memory controller, Am7990 Ethernet LAN
Controller, Chips & Technologies
PC-AT chipset, National Semiconductor DP8500 Graphics Engine.
[19] Design
of a Smart Card system: EEPROM-based data carrier, RF and IR transceivers, LCD,
I/O
controller using the Motorola MC68HC05/11 MCU. Prototype PCB and firmware development.
[18] Design
of a GDT Silicon Compiler library for embedded microcontroller applications
using
the 8051 instruction set.
[17] BiCMOS cell library and design flow, Dracula DRC, ERC, LVS
and LPE rules and set-up files.
[16] Design
of 256 Kbits and 64 Kbits SRAM in BiCMOS 1.0-mm technology (ECL/CML techniques).
[15] Design
of a RAMDAC equivalent to the Brooktree Bt458, with
125 MHz operating frequency,
in a CMOS 1.25-mm two-metal technology.
[14] Design
of a CMOS 1 Mbit EPROM (27C210 - 64KX16), first set of photomasks (IC Photomask
Tapeout) released to production.
[13] System
and logic design of a Virtual Instruction Processor, microcoded
to emulate
the instruction sets of the Motorola 68020 and Intel 80386
microprocessors.
[12] System
and logic design of a MIL-STD-1553B remote terminal and controller, bus
interface
and protocol management unit.
[11] Logic,
circuit design and IC layout of MIL-STD-1750A CMOS 16-bit microprocessor,
with FPU and interrupt controller for real-time
applications.
[10] Design
of mixed-signal, analog and digital CMOS IC for ordnance electronics. Low-power
watchdog and timer, integrated RF field rectifier and power
module, filters, transceiver,
frequency and phase modulator and demodulator, polynomial
counters, and output conditioner.
[9] Design
of a mixed-signal CMOS VLSI component for Rohm PBX equipment.
[8] Logic
and circuit design and IC layout of bipolar Schottky
TTL, ECL and I3L IC cell
libraries, SRAM, F9450 microprocessor, high-speed bus
interface, timer and ADC
[7] Design
and fabrication of CMOS IC and Si solar cells. Si process development:
photomasking, oxidation, dry and
wet etching, ion implantation and thermal diffusion,
Al metallization. MOS device
characterization and modeling.
[6] Analog
test instrumentation, Automation of measurements using a DEC LSI-11/02
microcomputer, an ADAC-1000 data acquisition board and a
GPIB-488 interface module.
System programming in Pascal, C and Assembly language.
[5] Design
of a Gas Chromatography Controller, using an Intel 8748 Microcontroller, and
Analog Devices ADC.
[4] Prototype
breadboard and firmware development: test and calibration, sequencing, PID
control loop, data acquisition, formatting and display.
[3] Data
acquisition and control system for hydraulic pumps, using an HP9825,
temperature,
vibration and pressure transducers and electronic
measurement equipment. Application
program in BASIC.
[2] Characterization
and modeling of GaAs MESFET and microwave IC.
[1] Microfabrication
and characterization of thin-film heterojunction GaAsInP
lasers and
fiber-optics coupler. Liquid-phase epitaxy,
photomasking and wet etching.
Education
Diplome d'Ingenieur
(BSEE & MSEE)
Ecole Superieure
d'Ingenieurs en Electronique et Electrotechnique
Paris, France - 1980.
MSEE
University of Cincinnati, Ohio - 1981.
Research work
* GaAs device modeling, digital
and RF analog circuits.
* GaAsInP
semiconductor laser.
* Data acquisition and electronic control circuits, Tin-film
Ceramic Hybrid Circuit and FR4
Printed Circuit Board, and system integration, automated product testing and
calibration.
* Si analog IC design and processing, semiconductor device manufacturing.
* Fabrication of MOS tunnel
diodes and solar cells.
MSEE Thesis:
" MOS Interface Trapped Charge
Characterization Using The AC Conductance Technique "
Membership
Institute of Electrical and
Electronic Engineers (www.ieee.com), since 1979.
Technology Alliance Bridge: www.tabridge.com, Silicon Valley, since
1996.
Other Activity
Expert Alpine Ski Instructor and Racing Coach, Auburn Ski Club (www.auburnskiclub.org).
Contact us for
consulting, to bring you help and to work on your success.
M: (530) 391-2978 Skype:
advlsi pierre@advlsi.com